Integrated Photonics IC
Date: Friday, April 28, 2017
Time: 2pm PST, 2pm AZT, 5pm EST
Please register by clicking on the link: Webinar or copy and pasting to your browser: https://attendee.gotowebinar.com/register/4749423321647453185
Gilles graduated from ESIEE (Ecole Supérieure D’Ingénieurs en Electronique et Electrotechnique), Paris, France in 1991.
He joined Cadence during his last year of study to work on his thesis (1989). He holds an Engineering Degree with a double major (Signal processing and component modeling).
After working in the field (including 8+ years in Japan and 2+ years in Russia), with customers in the areas of analog, Mixed-signal designs and custom layout, he joined the R&D team in San Jose. He lead the migration of the Virtuoso platform to the industry standard database (OpenAccess). He was instrumental in enabling the FinFet flow in the Virtuoso advanced node platform. About 4 years ago, he engaged into following the photonics industry, and in the last 2 years, lead the Virtuoso development and integration with Virtuoso two main partners, Lumerical and PhoeniX.
Looking forward at the next disturbance in the force is his job. He is currently learning about spin-tropics, spin-wave devices.
Gilles has about 20 patents, several as a single author.
Gilles hobbies include Lego, Pottery and doing things with my 2 twin boys (~6 yo).
The close integration of photonics ICs with their electrical counterpart has highlighted for many large companies the big gap in design methodology/productivity/predictability between the two. This has triggered an attempt to leverage the EDA investment (technical and methodology) to ramp up photonics IC design. This is very similar to what has happen on the manufacturing side, with Silicon Photonics taking advantages of all the advances made in CMOS manufacturing.
We will review several key examples of EDA methodologies (such as schematic driven layout) that can be used and leverage to increase photonics design productivity. At the same time, we will highlight some differences between the two domains, and how these are dealt with in a production environment such as Virtuoso.
Finally we will present some highlights of what can further be done to leverage the 3D, 2.5D IC methodology, signal integrity capabilities and packaging features of the electronics tools as the EPDA solution matures.